A key component in most synchronous digital systems is the oscillator. Conventionally, oscillators provide clock pulses which drive digital components. Since power dissipation in digital systems is highly dependent on the number of times digital logic within such components switches from an ON to OFF or OFF to ON state, controlling the clock pulses supplied to digital systems is a technique often used to reduce power consumption of battery powered digital devices.
One method is to provide two oscillators as described in U.S. Pat. No. 5,155,840. A main oscillator outputs clock pulses for high speed operation of a digital device while a sub-oscillator, operating at a lower frequency, also outputs clock pulses. A selector is provided to switch between the outputs of the main oscillator and the sub-oscillator.
During normal operation, the output of the main oscillator is selected to drive the digital device. When the digital device is in a power reducing mode, the output of the sub-oscillator is selected so that the clock pulse frequency is reduced, thus reducing the digital device's power consumption.
However, while the sub-oscillator reduces the power consumption of the digital device, the power consumed even when the sub-oscillator is selected is often wasted. Further, the main oscillator continues to oscillate and consume power even when the sub-oscillator is selected.